The present invention relates to the fabrication of semiconductor integrated circuits. More particularly, the present invention provides a technique, including a method and structure, for forming an isolation region and using double-charged implantation of a semiconductor substrate in the manufacture of complementary metal oxide silicon (CMOS) devices. But it can be recognized that the technique has a wide range of applicability. For instance, the technique can be applied to the manufacture of BiCMOS and the like.
In the manufacture of semiconductor integrated circuits, devices must be isolated from each other and from specific electrical paths. As device geometry becomes smaller, however, it is more difficult to keep such devices isolated using conventional techniques. A variety of these techniques have been proposed to keep such devices isolated. These techniques were made depending upon the type of integrated circuit being processed. For instance, these integrated circuits can use technologies such as bipolar, NMOS (N-type channel metal oxide silicon), PMOS (P-type channel metal oxide silicon), CMOS, BiCMOS (bipolar complementary metal oxide silicon), and the like.
In NMOS devices, for instance, a conventional technique for isolating devices is known as the local oxidation of silicon, commonly termed LOCOS. LOCOS generally uses steps of providing a semiconductor substrate. A layer of high quality oxide is defined overlying the substrate. A silicon nitride layer is defined overlying the oxide layer. Photolithography techniques define the silicon nitride layer leaving exposed regions of the oxide layer. The entire structure is placed into a furnace for oxidation to increases the thickness of the exposed oxide regions, which define the isolation regions. But the oxide regions underlying the nitride layer are substantially unoxidized, which provide a relatively flat surface region for the formation of a well region. The nitride layer is removed and devices can be formed in the flat surface region located between the isolation regions. Semiconductor devices such as MOS devices and the like are defined on the relatively flat surface region.
As device geometries reached sub-micron levels, however, it became necessary to replace the conventional LOCOS technique which has severe limitations for isolating the devices. In particular, the conventional LOCOS technique often did not effectively isolate the semiconductor devices from each other due to the harsher operating requirements, e.g, higher electric field, faster switch speeds, etc. In addition, as these devices became smaller, the feature size of the isolation regions provided by LOCOS was generally too large for the effective miniaturization of the devices.
Accordingly, other techniques have been proposed to overcome these and other limitations of the conventional LOCOS technique. These techniques, however, were extremely complicated and often added numerous process steps, which tended to reduce device yields and increase device turn-around-time. Examples of these techniques included modified LOCOS, silicon on insulator (SOI), silicon on sapphire (SOS), and others. A detailed discussion of these techniques can be found in Silicon Processing VLSI Era, Volume 2--Process Integration by Stanley Wolf, Lattice Press.
From the above, it is seen that a technique for fabricating a semiconductor isolation structure that is easy, reliable, and cost effective, is often desired.